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PRACE training course "HPC code optimization workshop" @ LRZ

begin
21.Jun.2018 09:00
end
22.Jun.2018 17:00
venue
LRZ Garching

In the ever-growing complexity of computer architectures, code optimization has become the main route to keep pace with hardware advancements and effectively make use of current and upcoming High Performance Computing systems.

Have you ever asked yourself:

  • Where does the performance of my application lay?
  • What is the maximum speed-up achievable on the architecture I am using?
  • Is my implementation matching the HPC objectives?

In this workshop, we will answer these questions and provide a unique opportunity to learn techniques, methods and solutions on how to improve code, how to enable the new hardware features and how to use the roofline model to visualize the potential benefits of an optimization process.

We will begin with a description of the latest micro-processor architectures and how the developers can efficiently use modern HPC hardware, in particular the vector units via SIMD programming and AVX-512 optimization and the memory hierarchy.

The attendees are then conducted along the optimization process by means of hands-on exercises and learn how to enable vectorization using simple pragmas and more effective techniques, like changing data layout and alignment.

The work is guided by the hints from the Intel® compiler reports, and using Intel® Advisor.

We provide also an N-body code, to support the described optimization solutions with practical hands-on.

The course is a PRACE training event.