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PATC Training course "Node-level performance engineering" @ LRZ

30.Nov.2017 09:00
01.Dec.2017 17:00
LRZ Garching

This course teaches performance engineering approaches on the compute node level. "Performance engineering" as we define it is more than employing tools to identify hotspots and bottlenecks. It is about developing a thorough understanding of the interactions between software and hardware. This process must start at the core, socket, and node level, where the code gets executed that does the actual computational work. Once the architectural requirements of a code are understood and correlated with performance measurements, the potential benefit of optimizations can often be predicted. We introduce a "holistic" node-level performance engineering strategy, apply it to different algorithms from computational science, and also show how an awareness of the performance features of an application may lead to notable reductions in power consumption.

The course is a PRACE Advanced Training Center event.

PATC training course "Introduction to hybrid programming in HPC" @ LRZ

18.Jan.2018 10:00
18.Jan.2018 17:00
LRZ Garching

Most HPC systems are clusters of shared memory nodes. Such SMP nodes can be small multi-core CPUs up to large many-core CPUs. Parallel programming may combine the distributed memory parallelization on the node interconnect (e.g., with MPI) with the shared memory parallelization inside of each node (e.g., with OpenMP or MPI-3.0 shared memory). This course analyzes the strengths and weaknesses of several parallel programming models on clusters of SMP nodes. Multi-socket-multi-core systems in highly parallel environments are given special consideration. MPI-3.0 has introduced a new shared memory programming interface, which can be combined with inter-node MPI communication. It can be used for direct neighbor accesses similar to OpenMP or for direct halo copies, and enables new hybrid programming models. These models are compared with various hybrid MPI+OpenMP approaches and pure MPI. Numerous case studies and micro-benchmarks demonstrate the performance-related aspects of hybrid programming.

Tools for hybrid programming such as thread/process placement support and performance analysis are presented in a "how-to" section. This course provides scientific training in Computational Science, and in addition, the scientific exchange of the participants among themselves.

The course is a PRACE Advanced Training Center event.

PATC training course "VI-HPS Tuning Workshop" @ LRZ

23.Apr.2018 09:00
27.Apr.2018 18:00
LRZ, Garching

This workshop organized by VI-HPS, LRZ and IT4Innovations for the PRACE Advanced Training Centre (PATC) at LRZ will:

  • give an overview of the VI-HPS programming tools suite
  • eexplain the functionality of individual tools, and how to use them effectively
  • offer hands-on experience and expert assistance using the tools

To foster the Czech-German collaboration in high performance computing, a contingent of places has been reserved for participants from the Czech Republic.

Programme Overview

Presentations and hands-on sessions are planned on the following topics (tbc.)

  • Setting up, welcome and introduction
  • Score-P instrumentation and measurement
  • Scalasca automated trace analysis
  • Vampir interactive trace analysis
  • Periscope/PTF automated performance analysis and optimisation
  • Extra-P automated performance modeling
  • Paraver/Extrae/Dimemas trace analysis and performance prediction
  • [k]cachegrind cache utilisation analysis
  • MAQAO performance analysis & optimisation
  • MUST runtime error detection for MPI
  • ARCHER runtime error detection for OpenMP
  • MAP+PR profiling and performance reports
  • A brief overview of the capabilities of these and associated tools is provided in the VI-HPS Tools Guide.

The workshop will be held in English and run from 09:00 to not later than 18:00 each day, with breaks for lunch and refreshments. The course is free of charge as the workshop is sponsored through the PRACE PATC program. All participants are responsible for their own travel and accommodation.

Participants are encouraged to prepare their own MPI, OpenMP and hybrid MPI+OpenMP parallel application codes for analysis.